1. Technical Field
This disclosure relates to semiconductor device inspection and testing and more particularly, to a system and method for determining yield impact of defects detected during in-line inspections.
2. Description of the Related Art
Defect data for semiconductor chips is typically collected by laser scanning, optical or scanning electron microscope (SEM). These techniques are employed as in-line defect inspections during the production of semiconductor devices. Defects may include a plurality of different events which may have totally different impacts on chip yield. The inspection techniques often provide a total count of the number of defects detected in each process step. Total count information does not enable a test engineer to assign a yield loss to defects detected at each particular process step.
It is a common standard in the semiconductor industry to inspect wafers at various times by employing optical and other inspection tools, such as the techniques described above, during production. These inspections provide data to shorten yield learning cycles significantly by reacting instantly to process problems. As a result, the process engineer obtains the number of defects per wafer, x-y coordinates of each defect and a set of parameters (different for different tools) specific for each particular defect. Any irregularities such as structural imperfections, particles, residuals or embedded foreign material are considered as defects. At the present time, this data is needed to approach benchmark yields for any product.
Correlation between in-line defect data and actual yield data is not accurate for small sample sizes (e.g. inaccurate one wafer only), or (because of the enormous memory sizes) the existing locally detailed yield data (e.g. bit maps) is not available for a sufficient sample of manufactured wafers. In-line defects are detected by the inspection techniques in between process steps for fabricating the semiconductor device. Actual defects are determined using electrical tests after the chips are fabricated. After electrical testing, some chips with defects may be salvaged by employing redundancies. Prior to employing the redundancies pre-fuse yield data may be obtained to determine if redundancies are needed or would improve yield.
Considering killing probabilities of any defect (probability p of the defect to kill the entire chip), the total defect count is comprised of events with all values of killing probabilities between 0 and 1. The total defect count information on its own or even including further characterizations for each single defect by optical microscopes, SEM, AFM, EDX (either manual review or automated defect classification) is not sufficient to assign an accurate number of yield loss to each process for complex chip designs (e.g. numerous redundancies on memory products). Further, the review of all inspected defects (even using automated classification) may delay the manufacturing process of semiconductor chips and yield learning cycles significantly.
To obtain useful yield impact information, it is desirable to correlate the actual defect data to electrical fails. Currently available yield correlation software packages distinguish from each other either in spatial resolution or in the algorithm which determines yield loss.
Regarding the spatial resolution, two extremes are available. While some yield correlation software may use wafer level defect and yield data, others take advantage of the spatial information of defect location on the wafer (i.e., accurate to within a given distance, for example, 15 microns, using the most accurate inspection tools) and correlate the spatial information of defect location to the most detailed available electrical information, that is, bitmap data. The advantage of the more detailed correlation with electrical bitmaps is the available amount of data which provides reasonable statistics for even a single wafer. The likelihood that a failed bit can be truly assigned to a defect found within a 15 xcexcm radius is for average yield and defect data above 99.99% (xcx9c1xc3x9710xe2x88x925). In addition, using specific electrical fail pattern information and available defect parameters improve the accuracy of this method. The disadvantage of this method is the excessive amount of data that has to be handled to monitor a production line. This confines the applicability of this method for volume wafer analysis.
On the other hand, using wafer level data provides reasonable accuracy only for huge samples ( greater than 50 wafer). This method is not useful for any lot or wafer level split analysis, which is needed for rapid yield learning.
Therefore a need exists for a system and method for correlating in-line defect data with pre-fuse yield data to determine a yield loss for each defect inspected wafer.
A method for determining yield impact of process steps for semiconductor wafers having a plurality of dies includes the steps of correlating defects on the dies to electrical failures on the dies to determine hits on the dies, computing kill rates for the dies based on hits for each inspection process, determining a number of dies to be killed by considering kill rates for the dies with hits to weight the defects of each die and determining a yield loss for each inspection process based on the number of dies to be killed and a total number of dies on the semiconductor wafer.
Another method for determining yield impact of process steps for semiconductor wafers having a plurality of dies includes the steps of inspecting a semiconductor wafer to determine defects, collecting defect data for each inspection process performed on the semiconductor wafer, the defect data including locations of defects on the semiconductor wafer, electrically testing the semiconductor wafer to determine electrical failures for dies on the semiconductor wafer, correlating the defects to the electrical failures to determine hits on the dies, computing kill rates for the dies based on hits for each inspection process, determining a number of dies to be killed by considering kill rates for the dies with hits to weight the defects of each die and determining a yield loss for each inspection process based on the number of dies to be killed and a total number of dies.
A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for determining yield impact of process steps for semiconductor wafers having a plurality of dies, the method steps include correlating defects on the dies to electrical failures on the dies to determine hits on the dies, computing kill rates for the dies based on hits for each inspection process, determining a number of dies to be killed by considering kill rates for the dies with hits to weight the defects of each die and determining a yield loss for each inspection process based on the number of dies to be killed and a total number of dies on the semiconductor wafer.
In other methods which may be implemented by a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for determining yield impact of process steps for semiconductor wafers, the step of correlating defects on the dies to electrical failures on the dies to determine hits on the dies may include the step of determining hits by assigning the defects of the dies to the electrical failures on the dies. The step of computing kill rates includes the step of computing kill rates for a given process inspection by dividing a number of hits on electrically failed dies by a number of defects for the process inspection may be included. The step of determining a number of dies to be killed by considering kill rates for the dies with hits to weight the defects of each die may include the steps of determining a number of dies to be killed by considering all dies with hits, initializing the number of dies to be killed to zero, modifying the number of dies to be killed by: calculating a kill rate ratio between a kill rate for each process inspection having hits and a sum of the kill rates for all process inspections having hits and adding the ratio to a previous number of dies to be killed, the previous number of dies to be killed being obtained at a previously considered die and repeating the step of modifying until all dies have been considered. The step of modifying is preferably performed using the formula:                               k          i                =                              k                          i              ,              previous                                +                      m            ·                                          r                i                                                              ∑                                      i                    =                    1                                    n                                ⁢                                  r                  i                                                                                        EQ        .                  xe2x80x83                ⁢        1            
where ki is a newly calculated number of dies to be killed for inspection process i, ki,previous is the previously calculated number of dies to be killed for the defects of inspection process i, ri is the kill rate for a given inspection process i, n is the number of processes which provided hits to the dies to be killed and m is the number of defects of a given type for a die being considered for the inspection process i. The step of determining a yield loss for each inspection process based on the number of dies to be killed and a total number of dies may include calculating the yield loss by dividing the number of dies to be killed for a given inspection process by the total number of dies of the semiconductor wafer. The method may further include the step of determining a killing probability yield loss for each inspection process based on the number of dies to be killed for each inspection process and a total number of defects for the inspection process.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.